1. Field of Invention
The present invention relates to a test key architecture. More particularly, the present invention relates to a test key architecture for evaluating the severity of stress-induced defects due to the formation of shallow trench isolation (STI) around integrated circuit devices and parasitic device effect.
2. Description of Related Art
Shallow trench isolation (STI) is a commonly used device isolation technique that is currently employed in the fabrication of CMOS memories. STI structures are formed by first carrying out an anisotropic dry etching operation to form a trench between a PMOS and an NMOS, and then filling in silicon dioxide (a non-conductive material) and polysilicon (a semiconductor material). The depth of the trench is generally deeper than the depth of the CMOS. Hence, the PMOS and NMOS within a CMOS can be successfully isolated so that latching between the two can be prevented, and the original level of integration for the CMOS can be maintained.
However, the formation of STI structures in static random access memory (SRAM) often leads to the occurrence of standby current failure. In particular, stress-induced defects due to the formation of STI structure and leakage current due to parasitic device effect are the major problems in SRAM/STI fabrication.
FIGS. 1A through 1C are diagrams illustrating the reason and points of origin of the parasitic device effect in a device. As shown in FIG. 1A, silicon dioxide 12 is deposited into the trench for forming an STI structure. Since two different types of materials (silicon substrate 10 and silicon dioxide 12) are used to form the trench, stresses 14 will be created at their junctions. Consequently, the upper surface 16 of the silicon dioxide layer 12 will form a slightly recessed cavity.
Next, as shown in FIG. 1B, a gate oxide layer and a polysilicon layer are deposited sequentially over the silicon substrate 10 to form a composite layer 18 (thereby forming an active region). Due to the creation of a geometric structure (arc-shaped structure) relative to point 20 inside the silicon substrate 10 around the STI construction, an electric field will tend to concentrate around that area.
FIG. 1C is a top view of the device and surrounding STI structure of FIG. 1B. As shown in FIG. 1C, a source region 22, a drain region 24 and a channel 26 between the source and the drain region are formed above the active region. The hatched areas represent the locations where the STI structures are formed. The internal point 20 of FIG. 1B becomes a line running along the intersection between the channel 26 and the STI structure in FIG. 1C, for example, lines 28 and 30. These resulting structures will bring out what is known as the parasitic device effect. When the device is operating in an off mode, a rather large leakage current appears.
FIG. 2 is a diagram illustrating the process of producing a stress-induced leakage current. In FIG. 2, parts that are the same as in FIG. 1C are labeled identically. As shown in FIG. 2, the long pass gate 32 covers a portion of the STI/active region. Due to the stress 34 that pulls in opposite direction, leakage cracks 36 induced by the stress will be created in areas between the channel 26 above the active region and the long pass gate 32. Consequently, a short-circuiting leakage current may be generated.
To illustrate the effect produced by cracks 36 in FIG. 2 better, a diagram showing the I-V characteristic curve of an operating device is drawn in FIG. 3. In FIG. 3, the horizontal axis represents the gate voltage V.sub.G (unit is Volt) while the vertical axis represents the drain current I.sub.D (unit is Amp). The solid line in FIG. 3 represents an ideal state. In the presence of stress-induced leakage current, off mode current (front portion of the curve in FIG. 3) will shoot up considerably as indicated by the dash line portion. The off mode current in FIG. 3 is shown to increase from the original 10.sup.-10 (A) to around 10.sup.-7 (A). Such an increase in off mode current will have a definite effect on the actual operation of the device.
Conventional test key architecture for measuring the effect of stress-induced defect and leakage current due to parasitic device effect usually includes an SRAM memory cell array and a number of MOS devices. FIG. 4 is a conventional test key architecture for measuring stress-induced leakage current and parasitic device effect.
As shown in FIG. 4, the test key architecture includes six transistors (T1.about.T6) that connect with bit line B and word line W, respectively. When a voltage is applied to the bit line and the word line W, leakage current Ig can be measured and analyzed. Ultimately, whether leakage current is due to stress defect or parasitic device effect can be determined. However, probability of having a leakage current is low. Therefore, an SRAM memory cell array having at least several thousand bits as well as many MOS device is needed in practice. Since these test keys occupy a large area, a difficult decision of whether to opt for timing efficiency or spatial efficiency must be made.
In light of the foregoing, there is a need to provide an improved test key architecture.